1. Field of the Invention
The invention is related generally to complementary metal-oxide-semiconductor CMOS circuits. It is more specifically directed to the design of output buffers in memory chips.
2. Description of the Related Art
CMOS amplifiers are conventionally constructed with a N-channel field effect transistor and a P-channel field effect transistor (FET) connected in series between ground and a positive voltage supply, Vcc. The source of the N-type transistor connects directly or indirectly to ground. The source of the opposing P-type transistor connects directly or indirectly to Vcc. The drains of the two transistors are connected together and their gates are also connected together.
During static operation, a gate voltage, V.sub.g, which develops at the gates of the transistors, remains at one or the other of Vcc and ground. This keeps one of the complementary transistors turned off and thereby minimizes the series current flowing from Vcc through the P and N transistors to ground.
During dynamic operation, the gate voltage V.sub.g transitions between Vcc and ground. As it does so, it passes through a range of values where both the N and P transistors are turned on. A relatively high magnitude of current surges through the transistors, passing from Vcc to ground during this time period. The current surge is referred to as "crowbar" current. Crowbar current is undesirable because it drains substantial amounts of energy from the power supply.
The range of gate voltage values where crowbar current flows is referred to as the crowbar region. The conventional method for minimizing power consumption due to crowbar flow is to minimize the amount of time spent by the gate voltage V.sub.g in the crowbar region. But this produces another problem, referred to as the L(di/dt) problem. The slope dV.sub.g /dt of the gate voltage V.sub.g becomes relatively large as time spent in the crowbar region is reduced. Since drain-to-source current, I.sub.DS, is a function of gate voltage, V.sub.g, the rate of change for drain-to-source current dI.sub.DS /dt increases as dV.sub.g /dt increases. An undesirable voltage surge, V=L(dI.sub.DS /dt) develops along the interconnect leads which couple the CMOS amplifier to the power supply. The surge is in response to the rate of change dV.sub.g /dt at the gates of the CMOS amplifier. L refers to the inductance of the interconnect leads. Interconnect inductance is particularly a problem at circuit portions where on-chip ground or power lines connect by way of relatively long conductors to the ground or power plane of a printed circuit board.
The compromise solution to both the crowbar problem and the Ldi/dt problem has been to minimize the time spent by gate voltage V.sub.g in the crowbar region while limiting the slope dV.sub.g /dt to a predefined maximum value.
There are circumstances, however, where such a compromise solution cannot be used. The design of adjacent circuitry might require the gate voltage V.sub.g to remain within the crowbar region for relatively long periods of time.
One example of this is encountered in the design of high-density static random-access memories (SRAM's) that rely on CMOS technology. Large parasitic capacitances develop either in the bit line structure of the memory device or in an intermediate data bus structure which couples a large number of memory cells to a final output buffer. Data readout time can be undesirably prolonged by the time required for charging and/or discharging the parasitic capacitors. To overcome this problem, the bit line and/or intermediate data bus is pre-charged in between each memory readout, to an amplifier switching point voltage, Vcc/2. This eases the burden placed on the sense amplifiers. The sense amplifiers have input lines coupled to the long bit lines and output lines coupled to the intermediate data bus. When the input and/or output lines are pre-charged to V.sub.cc /2, less time and/or energy is consumed by the sense amplifiers as they drive the intermediate data bus either to Vcc or ground as individual memory cells are addressed and their states are sensed.
A pre-charge approach of this type is disclosed for example, in a paper by Shinpei Kaayano, et al., entitled "265K.times.1/64K.times.4 CMOS SRAM's" IEEE Journal of Solid State Circuits, vol. SC-21, No. 5, Oct. 1986. A bus pre-charge circuit is provided at the input side of the chip's final output amplifiers.
Given the constraint that a switching point voltage, Vcc/2, is forced to appear on a line coupled to the gates of each CMOS output amplifier, the problem then becomes, how to transfer a sensed bit state through a CMOS amplifier in minimal time, while still minimizing crowbar current and the corresponding dI.sub.DS /dt rate of change.